One embodiment of the invention relates to a system LSI verification system and a system LSI verification program that verifies a processor module contained in a system LSI.
On account of the recent progress of digital equipments, the system LSI (Large Scale Integration) capable of implementing the functions that are required of respective digital equipments is needed. In contrast, with the diversification of the functions of the digital equipments, the functions that are required of the system LSI are also diverse. In order to deal with this diversification, in some cases the multi-processor construction having an extended function customized based on a common processor core to meet the process is employed.
In some cases this extended function is implemented by the configurable processor in which instructions, memory structures, and the like can be selected. Also, the provider of the configurable processor provides the system that outputs the hardware description that can be logically synthesized by pointing the configuration. According to such processor and system, the processor having the configuration that is most suitable for the application can be developed in a short term by pointing the optional instruction and the memory size.
Meanwhile, when the instruction set, and the like are changed in the system LSI, the software development tools such as complier, simulator, etc. must also be changed. Therefore, the new hardware description and the software development tools that deal with the new hardware must be generated by pointing the configuration.
In order to develop effectively the system LSI having such multi-processor construction, there is the system LSI development environment generating method set forth in JP-A-2003-323463. When the configuration pointing file in which the instruction operations of the processor are described is input by the method set forth in JP-A-2003-323463, RTL (Register Transfer Language), compiler, assembler, simulator, verification vector, and debugger are automatically constructed.
According to the method set forth in above Patent Literature 1, functions can be verified in unit of processor core in the processor module of the system LSI. However, such a problem lies that functions cannot be verified in unit of processor module that is contained in plural in the system LSI.
For this reason, the processor module verification environment must be generated every system LSI development that is associated with the application. Therefore, there are such a problem that, when a change of design specifications of the hardware and the firmware is caused, it takes much time to change the verification environment and the test program.
In addition, there exits such a problem that, when there are the portions whose verification environment is different mutually among a plurality of processor modules contained in one system LSI, change and management of the verification environment become more complicated.
Therefore, in order to increase a verification precision and reduce a term and a cost required for the verification, the method of reusing effectively the verification environment and the test program is requested.
Meanwhile, since the design proceeds along with the hierarchy of the architecture in the hardware development, the function verification is carried out separately at several stages every circuit scale or function, or is carried out in parallel with the hardware development. The verification environment containing the function that does the RTL simulation by compiling the test program applied to verify these hardwares is carried out by the method that is independent of respective verification steps. Accordingly, even when the test program is described in high-level language such as the C language, or the like, a change must be made in the test program to meet the individual verification environment. As a result, such a problem arises that the test program becomes complicated and also a huge cost is required to change the test program as the number of programs is increased.